IBM’s research into an analog artificial intelligence chip points to a different route for making deep learning more efficient. Instead of continually moving model parameters between memory and processors, the experimental design stores those parameters in memory components that can also perform computation. The distinction matters because data movement, rather than arithmetic alone, has become one of the largest costs in modern AI systems.
The chip described by IBM Research contains 64 analog in-memory compute cores and uses phase-change memory to represent neural-network weights. Published results suggest that this architecture can run important deep-learning workloads with competitive accuracy while reducing the energy spent shuttling data around a conventional digital system. It is still research hardware, but it clarifies why memory may become as important as faster processors in the next phase of AI infrastructure.
Data Movement Has Become an AI Bottleneck
Conventional computers separate storage from computation. Model weights are held in memory, transferred to a processor for a calculation, and then replaced by the next set of values. That arrangement is flexible and has supported decades of software development, but large neural networks repeat these transfers at enormous scale. Each individual movement seems small; together, they consume time, electrical power and memory bandwidth.
The problem grows as models become larger and are used more frequently. Adding faster arithmetic units does not remove the need to feed them data, so processors can spend part of their time waiting for information to arrive. This is sometimes described as the memory bottleneck. IBM’s work attacks that bottleneck directly by asking whether storage and calculation can happen in the same physical location, reducing the distance that model data must travel.
Phase-Change Memory Stores and Computes
IBM’s approach uses phase-change memory cells whose electrical conductance can represent the weights of a neural network. When signals pass through an array of these cells, the physics of the circuit performs many of the multiply-and-accumulate operations that dominate deep learning. The weights do not have to be fetched one by one and carried to a separate processor before every calculation.
That is the central appeal of analog in-memory computing: a physical property of the memory device becomes part of the computation. It trades the exact, discrete operations of a conventional digital chip for large numbers of parallel calculations performed inside memory. IBM’s 64-core design shows how several such arrays can be combined with supporting digital circuitry, creating a more complete system rather than a single laboratory memory array.
The Result Is About Efficiency and Accuracy
Analog computing is only useful for AI if it can preserve enough accuracy for real workloads. Physical devices vary, electrical noise affects results and memory conductance is not perfectly stable. IBM’s reported breakthrough is therefore not merely that the chip performs calculations in memory, but that it does so while retaining strong deep-learning accuracy. Careful calibration and accompanying digital components help compensate for the imperfections of analog hardware.
The work also demonstrates why efficiency should be evaluated at system level. A core may perform an operation cheaply, but conversion between digital and analog signals, control logic and communication among cores still cost energy. By integrating 64 cores and testing representative neural networks, the researchers provide a more realistic indication of what the technology can achieve. The results support the case for analog acceleration without suggesting that every part of an AI computer should become analog.
Research Hardware Still Faces a Long Deployment Path
A published prototype is not the same as a production chip. Commercial deployment would require reliable manufacturing, predictable behaviour over years of operation, software tools that map models onto the hardware and an economic advantage over rapidly improving GPUs and other accelerators. Developers would also need ways to handle model updates, precision requirements and workloads that do not fit the analog architecture naturally.
The most plausible future may therefore be hybrid. Digital processors can retain control, programmability and high-precision tasks, while analog in-memory units accelerate the repetitive matrix operations for which they are best suited. IBM’s chip makes that possibility more concrete. Its broader message is that the next efficiency gains in AI may come not only from shrinking transistors or adding processors, but from redesigning where computation happens.
Software will be as important as the device. Model developers are accustomed to digital arithmetic and mature accelerator libraries, so an analog platform must translate familiar neural networks into operations that respect its precision and hardware characteristics. Ideally, compilers and runtime tools would handle those differences rather than requiring every application team to become expert in phase-change materials.
The potential reward extends beyond lower electricity use. More efficient inference could place capable models in systems with limited cooling or power, while efficient training components could reduce the infrastructure required for experiments. Those outcomes remain prospective, but they explain why the prototype matters: it tests a different computing principle at a scale large enough to guide the next round of engineering.
Future comparisons should include accuracy, throughput, lifetime and total system energy on the same workloads. Analog hardware will earn a place in production only if its physical efficiency survives conversion overhead, manufacturing variation and the practical demands of software teams.
